Projects

Rust-based Flight Controller

Rust-based Flight Controller

RustSTM32EmbeddedRTOS

This project aims to achieve reliable flight performance with a custom built flight controller. It is built on top of the STM32F411 and a Rust based real-time framework, RTIC (Real-Time Interrupt-Driven Concurrency).

Embedded Team Lead @ UOttawa Autonomous Vehicle Team

Embedded Team Lead @ UOttawa Autonomous Vehicle Team

C++UARTROS2

Responsible for leading the embedded portion of the UOAV autonomous snowplow. Primary contribution was the integration of ROS2_control with custom C++ drivers to control the HDc2460 motor drivers.

NES Emulator

NES Emulator

CEmulationCPUSDL2DSP

Nintendo Entertainment System (NES) Emulator written in C. Features a cycle-accurate 6502 microprocessor capable of all legal instructions. Accurately replicates the PPU for authentic graphics, and employs digital signal processing (DSP) techniques for accurate audio.

CHIP-8 Emulator

CHIP-8 Emulator

CEmulation

Emulator written in C capable of emulating every CHIP-8 instruction. The binary can be used to play any CHIP-8 ROM with this project.

PyChess

PyChess

PythonPyGameDSA

PyChess is a Python-based chess game developed using the Pygame library. This project aimed to improve my coding skills by tackling the complexities of creating a functional chess game. I made use of concepts from data structures and algorithms for optimal time and space complexity.

Open Source Contributions

llvm

C++LLVM IR
[X86] Lower mathlib call ldexp into scalef when avx512 is enabled
  • Implemented custom lowering for ISD::FLDEXP to lower to VSCALEF/VSCALEFS instructions on AVX-512 targets
  • Widened f16 vectors to f32 when FP16 is not available
  • Widened 128-/256-bit vectors to full-width AVX-512 types when VLX is unavailable
[DAG] Add ISD::VECTOR_COMPRESS handling in computeKnownBits/ComputeNumSignBits
  • Added case handling for ISD::VECTOR_COMPRESS in computeKnownBits/ComputeNumSignBits, improving KnownBits propagation across backends
  • Added test cases for X86 AVX512, AArch64 SVE, and RISC-V RVV